Parallel Heterogeneous Energy efficient Real-time Multiprocessor Architecture
Parallel Heterogeneous Energy efficient Real-time Multiprocessor Architecture

Publications

SympA 2008 - Site web
S. Bilavarn, T. Dupont, N. Mounir, C. Belleudy, M. Auguin, A-M. Fouilliart
Une Analyse de Performances et de Consommation du Décodage H.264 sur ARM MPCore
SYMPosium en Architectures nouvelles de machines, SympA'2008, Friboug, Switzerland, 11/02/08-13/02/08

Abstract : Emerging trends in applications with the requirement of considerable computational performance and decreasing timeto- market have urged the need of multiprocessor systems. With the increase in number of processors there is an increased demand to efficiently control the energy and power budget of such embedded systems as well. Power management in embedded computing systems is achieved by actively changing the power consumption profile of the system by putting its components into such power/energy states which are sufficient to meet functionality requirements. Dynamic Power Management (DPM) strategies attempt to make decisions related to the choice of such states based on the available information at runtime. These strategies exploit the inherently present idleness (if any) in the application's behavior which is a priori unknown or non-stationary. This paper presents a novel DPM strategy called Assertive Dynamic Power Management (AsDPM) for real time applications. It is based on the idle time extraction from application's behavior and clustering to make appropriate decision for state-transition of processors in a multiprocessor real time system. Experimental results show that conventional DPM approaches often yield suboptimal, if not incorrect, performance in the presence of real time constraints whereas, the AsDPM strategy gives better energy consumption performance under the same constraints by 10.40%. Also, it reduces the number of state transitions by 74.85% and 59.76% for EDF and LLF scheduling policies respectively.
DSD 2008 - Site web
S. Bilavarn, C. Belleudy, M. Auguin, T. Dupont, A-M. Fouilliart
Multicore Implementation of H.264 Decoder with Power Management Considerations
11th Euromicro Conference on Digital System Design, DSD 2008, Parma, Italy, 03/09/08-05/09/08

Abstract : The intent of the recent H.264/AVC standard is to provide high quality video at low bit-rates and work effectively on a wide variety of networks and systems. A promising application is video broadcasting on mobile terminals but in practice, increased processing power and power management are required for embedded systems. In this paper, we consider an embedded multiprocessor to answer these requirements. This platform is the ARM11 MPCore, including up to four processors to bring enough processing power with dynamic voltage and frequency scaling techniques (DVFS). We present here the parallelisation and implementation analysis of a H.264 decoder using symmetric multiprocessing. We detail the performance and power consumption of the decoder in different conditions of voltage and frequency in a way to derive information for the exploitation of DVFS techniques in multiprocessor architectures.
VLSI-SOC 2008 - Site web
M.K. Bhatti, F. Muhammad, C. Belleudy, M. Auguin
Improving resource utilization under EDF-based mixed scheduling in multiprocessor real-time systems
16th IFIP/IEEE Int. Conf. on Very Large Scale Integration, VLSI-SOC'2008, Rhodes Island, Greece, 13/10/08-15/10/08

Abstract : The predominant approach of scheduling multiprocessor hard-real-time systems has been partitioned, in which each task is assigned statically (more or less) to one processor. Partitioned scheduling has the virtue of permitting schedulability to be verified using well-established monoprocessor schedulability analysis techniques for independent tasks. However, partitioned scheduling approach causes considerable under-utilization of the Multiprocessor System-on- Chip (MPSoC) platform resource. Alternative to partitioned scheduling is the global scheduling which permits the exploitation of platform capacity more efficiently by migrating tasks during their execution. This paper presents an approach for scheduling periodic real-time independent tasks and it's based on the idea of exploiting the under-utilization of MPSoC platform in a postpartitioned scenario by placing a global scheduler on top of all local schedulers of individual processors. This approach benefits from the theoretical basis available for partitioned scheduling approach and some of the advantages of having a global view of the total platform resource.
RTNS 2008 - Site web
D. Aoun, A.M. Déplanche, Y. Trinquet
Pfair scheduling improvement to reduce interprocessor migrations
16th Int. Conf. on Real-Time and Network Systems, RTNS'08, Rennes, France, 16/10/08-17/10/08

Abstract : Proportionate-fair (Pfair) scheduling is a particulary promising global scheduling technique for multiprocessor systems. Actually three Pfair scheduling algorithms have been proved optimal for scheduling periodic, sporadic and rate-based tasks on a real-time multiprocessor. However, task migration is unrestricted under Pfair scheduling. In the worst case, a task may be migrated each time it is scheduled. To correct this problem, we propose to complement initial Pfair scheduling algorithm by some heuristics that strive to minimize the total number of migrations. Experimental simulations are presented to evaluate and compare the proposed heuristics and we show that the number of migrations can be substantially reduced by adding these simple rules.
FTFC 2009 - Site web
K. Ben Chehida, R. David, F. Thabet, A.M. Déplanche, Y. Trinquet, R. Urunuela, M.K. Bhatti, C. Belleudy, M. Auguin, F. Broekaert, V. Seignole, A.M. Fouillart
Une approche globale de gestion de la consommation au niveau système pour des architectures MPSoC temps réel hétérogènes
8èmes Journées Faible Tension Faible Consommation, FTFC 2009, Neuchâtel, Suisse, 03/06/09-05/06/09

Abstract : The paper presents the assumptions together with the methodology that drive the Pherma project so as to be able to propose efficient electrical energy management techniques for heterogeneous multiprocessor architectures under real-time constraints. The electrical consumption optimization approach relies on a predictable architecture and a scheduling strategy that uses the execution resources efficiently. It combines an off-line method with an in-line one. Once its validation step achieved, it will be implemented inside an electrical energy management service inside the centralized control system.
Patmos 2009 - Site web
M. Bhatti, F. Muhammad, C. Belleudy, M. Auguin, O. Mbarek
"Assertive dynamic power management (AsDPM) strategy for globally scheduled real-time multiprocessor systems"
19th Int. Workshop on Power and Timing Modeling, Optimization and Simulation on Digital System Design, PATMOS 2009, Delft, The Nederlands, 09/09/09-11/09/09

Abstract : Emerging trends in applications with the requirement of considerable computational performance and decreasing time-to-market have urged the need of multiprocessor systems. With the increase in number of processors, there is an increased demand to efficiently control the energy and power budget of such embedded systems. Dynamic Power Management (DPM) strategies attempt to control this budget by actively changing the power consumption profile of the system. This paper presents a novel DPM strategy for real time applications. It is based on the extraction of inherently present idleness in application's behavior to make appropriate decisions for state-transition of processors in a multiprocessor system. Experimental results show that conventional DPM approaches often yield suboptimal, if not incorrect, performance in the presence of real time constraints. Our strategy gives better energy consumption performance under the same constraints by 10.40%. Also, it reduces the number of overall state transitions by 74.85% and 59.76% for EDF and LLF scheduling policies respectively.
Sympa 2009 - Site web
M. Bhatti, F. Muhammad, C. Belleudy, M. Auguin
"Controlling energy profile of real-time multiprocessor systems by anticipating workload at runtime"
SYMPosium en Architectures nouvelles de machines, Sympa 2009, Toulouse, France, 09/09/09-11/09/09

Abstract : Over the past several years, power/energy consciousness has emerged as an important criterion in the design of many real time embedded systems. Energy conservation in such systems is achieved by actively changing the power consumption profile of their components using energy-efficient scheduling algorithms. In this context, Dynamic Power Management (DPM) is a well-studied and experimented policy to reduce power/energy consumption by selectively putting idle components in energy-efficient states. The quality of these policies depends on the knowledge of target application's behavior, which in many cases is unknown a priori. Moreover, with the increase in number of processors there is an increased demand to efficiently control the energy and power budget of such embedded systems as well. This paper presents a novel DPM strategy called Assertive Dynamic Power Management (AsDPM) for real time applications. It is based on the idle time extraction from application's behavior and clustering to make appropriate decision for state-transition of processors in a multiprocessor real time system. Experimental results show that conventional DPM approaches often yield suboptimal, if not incorrect, performance in the presence of real time constraints whereas, the AsDPM strategy gives better energy consumption performance under the same constraints by 10.40%. Also, it reduces the number of state transitions by 74.85% and 59.76% for EDF and LLF scheduling policies respectively.
SAME 2009 - Site web
M. Bhatti, C. Belleudy, M. Auguin
"A dynamic power management strategy for globally scheduled real-time multiprocessor systmes"
Sophia Antipolis MicroElectronics, SAME 2009, Sophia Antipolis, France, 22/09/09-23/09/09

Abstract : Power management in embedded computing systems is achieved by actively changing the power consumption profile of the system by putting its components into such power/energy states which are sufficient to meet functionality requirements. Dynamic Power Management (DPM) strategies attempt to make decisions related to the choice of such states based on the available information at runtime. DPM strategies exploit the inherently present idleness (if any) in the application's behavior which is a priori unknown or non-stationary. This paper presents a novel DPM strategy called Assertive Dynamic Power Management (AsDPM) for real time applications. It is based on the idle time clustering and clairvoyance to make appropriate decision for state-switch of a MP-System component.
ICECS 2009 - Site web
M. Bhatti, C. Belleudy, M. Auguin
"A framework for offline optimization of enregy consumption in real-time multiprocessor system-on-chip"
IEEE Int. Conference on Electronics, Circuits and Systems, ICECS 2009, Tunisia, 11/12/09-13/12/09

Abstract : Emerging trends in applications with the requirement of considerable computational capacity and decreasing time-to-market have urged the need of multiprocessor systems. With the advent of multiprocessor systems, there is an increased demand to efficiently control their energy and power budget. As the technology scales to increasingly smaller feature sizes, the static power consumption is expected to grow exponentially which will also contribute a significant part in system's total power consumption. Moreover, modern-day applications are complex and offer limited extractable parallelism which eventually leads to poor performance by existing energy optimization techniques. In this paper, we present a two-fold framework for energy optimization. In the first step, we provide an algorithm, called MPSched (Minimum Processors for Schedulability), to optimize on the number of processors needed to fulfill execution requirement of target application. In the second step, we perform Static Voltage and Frequency Scaling (SVFS) to achieve an optimal energy profile of the system.
EUROSIM 2010 - Site web
R. Urunuela, A.M. Déplanche, Y. Trinquet
"Simulation for multiprocessor real-time scheduling evaluation"
I7th EUROSIM Congress on Modelling and Simulation, Prague, Czech Republic, 06/09/10-10/09/10

Abstract : The increasing complexity of the hardware multiprocessor architectures as well as of the real-time applications they support makes very difficult even impossible to apply the theoretical real-time multiprocessor scheduling results currently available. Thus, so as to be able to evaluate and compare real-time multiprocessor scheduling strategies on their schedulability performance as well as energy efficiency, we have preferred a simulation approach and are developing an open and flexible multiprocessor scheduling simulation and evaluation platform called STORM ("Simulation TOol for Real-time Multiprocessor scheduling"). This paper presents the simulator on which STORM relies and that is able to simulate accurately the behaviour of those (hardware and software) elements that act upon the performances of such systems. An example is given to illustrate such a performance evaluation.
ETFA 2010 - Site web
R. Urunuela, A.M. Déplanche, Y. Trinquet
"STORM - A simulation tool for real-time multiprocessor scheduling evaluation"
15th IEEE International Conference on Emerging Technologies and Factory Automation, Bilbao, Spain, 13/09/10-16/09/10

Abstract : The increasing complexity of the hardware multiprocessor architectures as well as of the real-time applications they support makes very difficult even impossible to apply the theoretical real-time multiprocessor scheduling results currently available. Thus, so as to be able to evaluate and compare real-time multiprocessor scheduling strategies on their schedulability performance as well as energy efficiency, we have preferred a simulation approach and are developing an open and flexible multiprocessor scheduling simulation and evaluation platform called STORM ("Simulation TOol for Real-time Multiprocessor scheduling"). After an overview of the related available software simulation tools together with the motivations of our work, this paper presents the simulator on which STORM relies and that is able to simulate accurately the behaviour of those (hardware and software) elements that act upon the performances of a multiprocessor system. At first, the presentation is made from the user point of view: input data, graphical user interface with its commands, output results. Then the functional architecture of the simulator is explained: simulation kernel, simulation (hardware, software and system) entities, behaviour and interactions between these kernel and entities. An example (inspired of a H264 image decoder) is given to illustrate the capabilities of our tool.
DASIP 2010 - Site web
M. Bhatti, C. Belleudy, M. Auguin
"An inter-task real-time DVFS scheme for multiprocessor embedded systems"
2010 Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, United Kingdom, 26/10/10-28/10/10

Abstract : In this paper, we have addressed energy-efficient scheduling of real time applications intended to be executed on multiprocessor systems. Our proposed technique, called Deterministic Stretch-to-Fit (DSF) technique, is based on inter-task real time dynamic voltage and frequency scaling (RT-DVFS). It mainly comprises of three components. Firstly, we propose an online algorithm to reclaim energy by adapting to the variations in actual workload of target application tasks. Secondly, we extend our online algorithm with an adaptive and speculative speed adjustment mechanism. This mechanism anticipates early completion of future task instances based on the information of their average workload. Thirdly, we propose a one-task extension technique for multi-task multiprocessor systems. No real time constraints of target application are violated while applying our proposed technique. Simulation results show that our online slack reclamation algorithm alone gives up to 53% gains on energy consumption and our extended speculative speed adjustment mechanism, along with the one-task extension technique, gives additional gains, reaching a theoretical low-bound on the scalable frequency and voltage.
TSI 2010
S. Bilavarn, C. Belleudy, M. Auguin, T. Dupont, A.M. Fouillart
"Implantation d'un décodeur H.264 sur plateforme multiprocesseur avec gestion énergétique"
Technique et Science Informatiques Volume 29/2 - 2010 - pp.201-224

Abstract : Embedded systems have moved recently towards multiprocessor architectures to support the level of performance required by new mobile applications. For those systems, power is a sensitive aspect that points to the need for study and developement of efficient power management strategies. This paper presents a concrete case study in one of the primarily concerned application domain: multimedia and video broadcasting. It reports the implementation details of a H.264/AVC decoder on a multiprocessor platform (ARM11 MPCore EB) considering in particular the problem of power reduction using online and offline techniques of power management (DVFS, DPM).