Parallel Heterogeneous Energy efficient Real-time Multiprocessor Architecture
Parallel Heterogeneous Energy efficient Real-time Multiprocessor Architecture


The increasing complexity of embedded and mobile systems requires MPSOC architectures to permit the exploitation of parallelism with respect to the performance requirements. As a consequence, modelling the behaviour of those architectures results in a much more difficult process to obtain solutions verifying “a priori” some execution deadline and/or throughput constraints. Energy optimisation in this context becomes a very sensitive issue regarding unreliable prediction and estimation of behaviours. This design trend goes against the energy reduction criteria, which is of growing importance in mobile applications. To address this key issue, the PHERMA project (Parallel Heterogeneous Energy efficient Real-time Multiprocessor Architecture) proposes to reconsider the control scheme (RTOS) in a MPSOC architecture :
  • To propose a performant Sw/Hw architecture model with deterministic behaviours in a way to guaranty maximum response times ;
  • To adapt and ease the schedulability analysis on the basis of this architectural model to hold an “a priori” verification of task deadline meeting ;
  • To propose methods for offline and online optimization of power consumption considering this architectural model.
The PHERMA project is aiming to propose a design and execution environment for a new architecture based on a heterogeneous CMP execution model called SCMP (Scalable Chip Multi Processing, developed by the CEA) that supports dynamic migration and preemption of tasks. It is seen by the CPU as a coprocessor dedicated to the control and execution of critical applications whereas the CPU is in charge of interface management and general purpose processing. To control the execution of these critical applications, the PHERMA project is aiming to implement some Operating System (OS) services on HW to allow a scalable and deterministic OS behaviour (in terms of response time). Scalable to cope with the rising number of embedded cores on the emerging Multi-Processor System on a Chip (MPSoC), and deterministic in the context of real time and power aware system design. Developing such predictable high performance real-time systems requires to investigate appropriate scheduling policies together with their schedulability analysis so as to guarantee that timing requirements are always met.
Our proposal consists in revisiting the management organization in a MPSoC architecture so that:

i) the overall efficiency of the management is really augmented,
ii) the power awareness and the real-time criteria are handled jointly,

Our method is based on a virtualization of the MPSoC architecture as a « parallel multi-tasking mono-processor ». It can be seen as a homogeneous view of the task/thread and inter-processor communication that are generally managed in different control layers in current parallel architectures. In our virtualized MPSoC, tasks and communications are application components that have to be scheduled by a single management layer (scheduler) and executed by the units of the architecture. A single scheduler for the tasks and communications, allow a virtualization of the architecture as a « parallel multi-tasking mono-processor ». This point is very important since it gives the opportunity to consider traditional monoprocessor-based schedulability analysis in order to guaranty real time execution constraints, provided that Worst Case Execution Time (WCET) values for tasks and communications are known.
In numerous systems, power/energy consumption becomes an objective of the same importance than the real time application's tasks execution: for example a maximum consumption of 3W (constraint due to battery technology) is generally considered by designers of mobile phones, whatever the number and the types of functionalities integrated in the phone. Furthermore, future MPSoCs include an increasing part of memory that will contribute mainly to the overall power consumption of the system. Managing the power modes of a multi-banks memory is of prime importance to avoid an augmentation of the power consumption due to the memory while reduction of frequency and voltage (DVFS) are applied to the processor part.
Project structure
The project is divided into 5 sub-projects (SP) as depicted in the following figure. The first SP (SP1) concerns the management of the project, the definition of the architecture model and the validation plan. Two SPs are dedicated to the technical tasks of the project, SP4 to the validation of the results and the last one to the dissemination of the results.
More specifically the four SPs are the following:
  • SP1: Scientific and Administrative management of the project
  • SP2: Scheduling, schedulability analysis and low power techniques for MPSOC
  • SP3: HW platform definition and modelling
  • SP4: Platform and low-power techniques validation and prototyping
  • SP5: Dissemination

Expected scientific and technological impact
Expected impact could be very significant since the PHERMA project addresses a key point in high performance real time and power aware system design: some methodologies exist for verifying properties or correctness of a real time system model but there is a lack of architecture models and design/mapping methods that permit a seamless implementation while preserving the expected behaviours and power saving scenarios. With the results of the PHERMA project, validated on a prototype, we will demonstrate that a deterministic, low power parallel system can be designed such that

i) the resource utilization is optimized (busy rate of resources is increased, minimization of the oversizing of the architecture due to a lower pessimism in models),
ii) power consumption is reduced (use of offline and online strategies) and
iii) robustness of solutions is increased (higher determinism in the architecture) thus limiting the validation costs.

These results are of particular importance for industrials which target for example the market of (mobile) advanced embedded systems. The PHERMA project will not provide a complete and general solution to this global problem but we are convinced that the project could significantly contribute to the emergence of further research projects addressing this important key topic: improving the performance/determinism trade-off of the architecture, better relationship between the schedulability analysis models/methods and the architecture.
Expected industrial and economical impact
Products developed in the next years by THALES Communications will be mobile, multi-protocols and will support numerous services (image, video, JPEG2000, MPEG2, MPEG4, H264). Consumption will be a major constraint for these products.
Modern mobile equipments take advantage of multiprocessor architectures to achieve their performance requirements indirectly dependent on the variety of information being processed. For such heterogeneous and increasingly complex systems, the classical energy optimization and management techniques have to be reconsidered.
For this reason, overcoming power issues in modern embedded system should be tackled globally from coherent OS development perspectives.
For THALES Communications, the PHERMA project will allow to make use of innovative techniques for optimising the consumption. It will bring effective solutions to implement real time and embedded software.